This invention relates generally to memory cells and more particularly to memory cells for use in digital shift registers.
A digital shift register typically comprises several serially coupled memory cells, the number of which corresponds to the bit capability of the shift register. In an article by M. Rocchi and B. Gabillard entitled "GaAs Digital Dynamic IC's for Applications up to 10 GHz", appearing in the IEEE Journal of Solid-State Circuits, Vol. SC-18, No. 3, June, 1983, the memory cells are described as each comprising a pair of serially coupled, inverting storage circuits, with a transmission gate disposed at the input of each storage circuit to control signal flow into that circuit. The transmission gates are fed by complementary clock signals to switch a selected one of the gates between a conducting state, to clock a signal through the transmission gate and into the storage circuit associated therewith, and a nonconducting state, to inhibit a signal from coupling into the associated storage circuit. A pair of such inverting storage circuits is used in each memory cell so that the output signal from the memory cell has the same logic polarity as the input signal fed to the memory cell.
As it is desirable that digital shift registers operate at the highest possible shifting rate, the pair of storage circuits and the transmission gates of the memory cell have been fabricated using metal electrode field-effect-transistors (MESFETs) on gallium arsenide (GaAs) substrate, as described by the above-referenced article. Gallium arsenide is preferred over other substrates, such as silicon, because of its higher carrier mobility, allowing for more rapid data shifting. Each storage circuit comprises a MESFET, connected as an inverter, which stores in the gate-to-drain and gate-to-source capacitances thereof the electric charge corresponding to the level of a signal coupled to the gate electrode at the time such signal is clocked through the transmission gate connected at the input of the storage circuit. The inverting/charge storing MESFET also produces at the drain electrode thereof an amplified and logically inverted signal from the signal clocked through the transmission gate, coupled to the gate electrode and stored in the capacitances of such MESFET. The storage circuit also includes a level shifter, coupled to the drain electrode of the inverting/charge storing MESFET, which comprises a source-follower MESFET, and a series of level-shifting diodes. The level shifter converts the level of the amplified and inverted signal made available at the drain electrode of the inverting/charge storing MESFET to a level suitable for driving the next storage circuit of the memory cell.
The memory cells' transmission gates are also MESFETs. The gate electrodes of the transmission gates connected at the inputs of the pair of storage circuits of each memory cell are fed by a pair of complementary clock signals. The use of complementary clocks prevents data entering the memory cell from coupling through the pair of storage circuits and exiting the memory cell within the duration of a single clock pulse. Thus, the shifting of data through a memory cell is a two-step process: (1) the first clock signal is applied to the gate electrode of the transmission gate MESFET connected at the input of the first one of the pair of storage circuits, switching the transmission gate to a conducting state to couple a signal into the first storage circuit, where the signal is stored, amplified, inverted and level-shifted; and, (2) the second, complementary clock signal is applied to the gate electrode of the transmission gate MESFET connected at the input of the second one of the pair of storage circuits, switching the transmission gate to a conducting state to couple the level-shifted output of the first storage circuit into the second one of the pair of storage circuits, where the signal is stored, amplified, inverted and level-shifted. The level shifted output of the second storage circuit is the output data signal of the memory cell, shifted in time from the input data signal by the complementary first and second clock signals.
While the above-described memory cell operates at sufficient shifting rates in some applications, it is desirable in many other applications to design a memory cell capable of even higher shifting rates to enable shift registers incorporating such memory cells to operate at the maximum possible data shift rates.